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Browse Prior Art Database

PNP Transistor Process

IP.com Disclosure Number: IPCOM000051013D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Bergeron, DL: AUTHOR [+5]

Abstract

A well-controlled fabrication process is provided for making a high speed analog double-diffused PNP transistor.

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PNP Transistor Process

A well-controlled fabrication process is provided for making a high speed analog double-diffused PNP transistor.

An N type epitaxial layer 10 is grown on a P type semiconductor substrate 12, with an N+ type subcollector region 14 formed at the junction of the layer 10 and substrate 12 in a known manner, as shown in Fig. 1. Arsenic is implanted into the surface of layer 10 with a dose of 1.5x10/12/ ions/cm/2/ at 50 KeV for surface tailoring purposes. A silicon dioxide layer 16 having a thickness of about 3700 angstroms is grown over the surface of layer 10, and an N+ type reach- through 18 is formed between the surface of layer 10 and subcollector region 14.

A photoresist mask 20, at least 2 microns thick, having an opening 22 is formed over the silicon dioxide layer 16. To form the collector of the PNP transistor, boron is implanted into implant region 24 at the surface of epitaxial layer 10 through opening 22 with a dose of 8x10/12/ions/cm/2/ at 340 KeV. Photoresist mask 20 is now removed and a base mask is used to form an opening 26 in silicon dioxide layer 16, as shown in Fig. 2.

Using a nitrogen and oxygen mixed carrier Bas bubbled through P0C1(3), phosphorous is diffused into the surface of epitaxial layer 10 through opening 26 at 800 degrees C. A subsequent argon ambient drive-in at 1,050 degrees C forms the N+ base region 28, along with collector region 24', as illustrated in Fig.
3. By using the argon ambient drive-in, only a thin l...