Browse Prior Art Database

NPN Transistor Process

IP.com Disclosure Number: IPCOM000051014D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Bergeron, DL: AUTHOR [+5]

Abstract

A well-controlled fabrication process is provided for making a high speed analog NPN transistor.

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NPN Transistor Process

A well-controlled fabrication process is provided for making a high speed analog NPN transistor.

An N type epitaxial layer 10 is grown on a P type semiconductor substrate 12, with an N+ type subcollector region 14 formed at the junction of the layer 10 and substrate 12 in a known manner, as shown in Fig. 1. A silicon dioxide layer 16 having a thickness of about 3700 angstroms is grown over the surface of layer 10, and an N type reach-through 18 is formed between the surface of layer 10 and subcollector region 14.

An opening 20 is formed in silicon dioxide layer 16 in any known manner, as indicated in Fig. 1, and a very uniform layer of silicon dioxide 22, approximately 1700 angstroms thick, is regrown over the surface of layer 10 at opening 20, as shown in Fig. 2. A photoresist layer 24, approximately 2 microns thick, having an opening 26 aligned within opening 20 in layer 16, is formed over silicon dioxide layer 16. A first boron implant having a dose 0.8 to 1.0x10/13/ ions/cm/2/ at 20 KeV and a second boron implant having a dose of 6 to 10x10/12/ ions/cm/2/ at 330 KeV are introduced into the surface of epitaxial layer 10 through opening 26 and uniform silicon dioxide layer 22 for forming the base region of the NPN transistor, as indicated in Fig. 3.

Photoresist layer 24 is removed and a layer of silicon nitride 28 having a thickness of about 850 angstroms is deposited by a low pressure chemical vapor deposition technique over silicon diox...