Browse Prior Art Database

Self Aligned Schottky Barrier Diode Guard Ring

IP.com Disclosure Number: IPCOM000051015D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Agusta, B: AUTHOR [+2]

Abstract

A method is provided for making a Schottky-barrier diode having a self aligned guard ring without increasing the overall size of the diode at the surface of a semiconductor wafer or substrate.

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Self Aligned Schottky Barrier Diode Guard Ring

A method is provided for making a Schottky-barrier diode having a self aligned guard ring without increasing the overall size of the diode at the surface of a semiconductor wafer or substrate.

As shown in Fig. 1, a silicon wafer or substrate 10 having, s.g., an N type conductivity, has two differentially etchable insulating layers, e.g., silicon dioxide 12, formed on the surface thereof with a second layer 14, e.g., silicon nitride, disposed over insulating layer 12. By known photo-masking and etching techniques, an opening 16 is formed in silicon nitride layer 14 and then an opening corresponding to opening 16 is formed in insulating layer 12 to expose the surface of substrate 10. The opening in insulating layer 12 is made larger than the opening in silicon nitride layer 14 so as to provide an overhanging or protruding segment 18 in silicon nitride layer 14. A P type conductivity region 20 is formed in substrate 10 by diffusing or ion implanting, e.g., boron, into substrate
10. The implant may be performed from several directions in order to extend P region 20 along the entire exposed surface of substrate 10 defined by the opening in insulating layer 12. A thermal annealing cycle may follow the implant, if desired. A Schottky metal 22, e.g., palladium or platinum, is then deposited through and defined by the opening in silicon nitride layer 14.

The reaction of the metal 22 with the silicon substrate 10 at elevated t...