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Reducing the Device Size of Polysilicon Base Transistor

IP.com Disclosure Number: IPCOM000051022D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

Two methods are disclosed to reduce the size of a shallow-junction "poly-base" transistor. Both methods achieve this by situating the emitter and collector reachthrough/collector contact windows close to each other in a self aligned manner.

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Reducing the Device Size of Polysilicon Base Transistor

Two methods are disclosed to reduce the size of a shallow-junction "poly- base" transistor. Both methods achieve this by situating the emitter and collector reachthrough/collector contact windows close to each other in a self aligned manner.

METHOD 1. 1. Following the early portion of a standard "poly-base" process, obtain the device structure shown in Fig. 1. N/+/ layer 4 is the sub- collector region in a P/-/ wafer, being surrounded by deep trench isolation (DTI)
10. N/-/ layer 8 was formed using epitaxy. At the top of the N/-/ epi layer 8 and DTI, patterned insulation layers 12 of SiO(2) and 14 of Si(3)N(4) were formed. A layer 16 of polycrystalline silicon material (referred to below as poly 16), which was doped P/+/ type preferably through ion implantation, was then deposited. SiO(2) and Si(3)N(4) insulation layers 18 and 20, respectively, were next formed above poly 16.

2. Using photoresist mask 22 and reactive ion etching (RIE), patterns are formed in Si(3)N(4 /SiO(2) layers 20/18 and poly 16, as shown in Fig. 2.

3. Retaining resist mask 22, a new blockout resist mask 24 is formed. Using appropriate energy, an N/+/ impurity region 25 is ion-implanted in the exposed silicon, as illustrated in Fig. 3. Using an etchant, for example, HF:HNO :CH(3)C00H=1:3:8, which preferentially etches P/+/ poly and leaves N/-3/ silicon substantially unharmed, etch poly 16 by a suitable amount, as further illustrated in Fig. 3.

4. After removing all resist, deposit pyrolytical SiO(2) layer 26, and using vertically directional RIE, obtain the structure of Fig. 4.

5. Using a new blockout resist mask, ion implant a P-type impurity in exposed silicon to form the intrinsic base. Remove the resist mask.

6. Deposit an N/+/ impurity in the exposed portions of silicon to form emitter region 30 and collector reachthrough region 30'. After subjecting the wafer to a suitable heat cycle, the structure of Fig. 5 is obtained. In this figure, P region 28 is the base whose "intrinsic" portion is formed by the P impurity of step 5 above and whose "extrinsic" portion is formed by the downward diffusion of the P impurity in poly 16. Connected N/+/ regions 25, 30' form the complete collector reachthrough region. The contact window in the insulation layers 20 and 18 is opened next for metal contact to poly 16. The device structure is then completed by forming PtSi at the exposed silicon contact regions and forming A1/Cu metallization patterns in a conventional manner.

From the above outlined process a transistor structure results wherein the emitter and collector reachthrough/collector contact windows are situated approximately only one poly width away from each other in a self-aligned manner. Further, the extrinsic base and collector reach-through are precisely prevented from coming too close to each other. In the absence of the lateral etching of poly 16...