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Method of Fabricating a Compact Transistor Structure

IP.com Disclosure Number: IPCOM000051024D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

This is a proposal for a very compact bipolar transistor structure with polysilicon base and collector contacts. A method for realizing this transistor structure is described with reference to Figs. 1-7, with a cross-section of the resulting transistor structure being shown in Fig. 7. Geometries of some of the important masks that are used in the described method are shown in Fig. 8.

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Method of Fabricating a Compact Transistor Structure

This is a proposal for a very compact bipolar transistor structure with polysilicon base and collector contacts. A method for realizing this transistor structure is described with reference to Figs. 1-7, with a cross-section of the resulting transistor structure being shown in Fig. 7. Geometries of some of the important masks that are used in the described method are shown in Fig. 8.

The preferred process is as follows:

1. Start with a P- substrate, and, in a conventional fashion,

form in it N+ subcollector 4 and P+ subisolation 6. Grow

about 2 Mum thick N- epitaxial layer 8 and about 1,500

Angstroms SiO(2) 10 on the substrate. Use mask "D", and,

in a conventional fashion, selectively form about 1 micron

recessed oxide isolation (ROI) 12. Deposit an approximately

1500 Angstroms thick layer 14 of Si(3)N(4), and, using the

"F" mask form a corresponding pattern in the Si(3)N(4). By

means of mask "C", open windows in the SiO(2) 10 and form N+

collector reach-through region 17 through diffusion

technique. A cross-section of the transistor structure at

this stage of conventional processing is depicted in Fig. 1.

2. Deposit approximately 7,000 Angstroms polysilicon 18 and

about 1500 A Si(3)N(4) 22. Using photoresist mask "F(2)",

selectively P+ dope polysilicon 18 through ion implantation

(Fig. 2). The ion implantation may alternatively be

carried out before the deposition of Si(3)N(4)22. In Fig.

2, the p+ doped portion of polysilicon 18 is identified

as 20.

3. Using mask "G" and reactive ion etching (RIE), form islands

in the composite structure of Si(3)N(4) 22 and polysilicon

18/20 and proceed to etch exposed SiO(2) 10 (Fig. 3).

4. Using a block-out mask " photoresist 23, form about 0.5

Mum laterally deep undercut in SiO(2) 10, as illustrated in

Fig. 4. BHF acid is a suitable selective etchant for this

purpose.

5. Through chemical vapor deposition (CVD), form a layer of

about 2,000 Angstroms polysilicon. Due to the conformal

deposition inherent in CVD, the undercut region is filled by

the polysilicon. Through thermal oxidation, convert the

polysilicon into SiO(2) 40 excepting that portion of

polysilicon which filled the undercut regions (Fig. 5). The

undercut region filled with polysilicon is identified as 41

in Fig. 5.

6. Remove SiO(2) 4...