Browse Prior Art Database

Automatic Generation of Bit Patterns for Array Testing

IP.com Disclosure Number: IPCOM000051026D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Peters, RM: AUTHOR [+3]

Abstract

A software process is provided for automatically generating test patterns which will ultimately be used to test array chips on array testers which incorporate commercially available word generator hardware. As carried out presently, the process involves manual creation of the test pattern which may take up to six man months for a single part number.

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Automatic Generation of Bit Patterns for Array Testing

A software process is provided for automatically generating test patterns which will ultimately be used to test array chips on array testers which incorporate commercially available word generator hardware. As carried out presently, the process involves manual creation of the test pattern which may take up to six man months for a single part number.

The process described here presupposes an architecture similar to the TSO (Time Sharing Option) system shown in Fig. 1. Input to the process involves commands to TSO terminal 1 containing two types of information. The first type of information involves chip description, and the second type of information involves pattern description. The digitized specification data from block 3 is then employed in conjunction with the known DC/AC test environment, as uses bit pattern generator 9 in conjunction with AC program generator 11 to automatically generate test patterns. The AC and DC programs respectively generated in the right- and left-hand branches of the system shown in Fig. 1 are assembled in tester assembler 13 whereby commands are assembled for operating the array testers (not shown).

Input commands to the system are "high level" which, as used here, means they cannot directly drive either the array testers or the tester assembler. "High level", as also used here, means that the commands have meaning independent of other commands. Figs. 2A and 2B contain examples of typical high level commands that may be employed. The sequencing of the input commands is such that the chip description commands are processed first, followed by the pattern description commands. Critical chip description data for array pattern generation are dimensional data (i.e., number of word and bit addresses) and the number of data lines.

The output of bit pattern generator 9 in Fig. 1 comprises bit pattern data and control information higher than, but close to, the format of the commercial word generator hardware A and B matrices. This data, shown by block 15, is used as input to tester assembler 13 whic...