Browse Prior Art Database

L2 Receiver Latch Circuit

IP.com Disclosure Number: IPCOM000051027D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+3]

Abstract

The disclosed L2 receiver latch circuit has particular utility in an electronic chip in place test (ECIPT) (1) system conforming to Level Sensitive Scan Design (LSSD) (2) rules.

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L2 Receiver Latch Circuit

The disclosed L2 receiver latch circuit has particular utility in an electronic chip in place test (ECIPT) (1) system conforming to Level Sensitive Scan Design (LSSD) (2) rules.

This article proposes a unique latch which incorporates the receiver as an integral part. By incorporating the receiver as part of the latch, the delay of AI#4 in Fig. 1 is eliminated and its area and power are saved.

The operation of the proposed latch (Fig. 2) is as follows: One input of a two- input receiver is tied directly to the chip boundary input position, while the other input is used as a +C clock on chip signal input to latch. The output of the receiver is the -L2 output and is dotted with the node of the A1#3 output (-L2), forming the polarity hold latch of Fig. 2. Block A1#4 delay, area and power are saved using this technique.

The data path's performance is again equal to the design without ECIPT while offering the many advantages of an ECIPT design. References
(1) P. Goel and M. T. McMahon, "Electronic Chip in Place Test,"

19th Design Automation Conference Proceedings, pages 482-488,

June 14, 15 and 16, 1982, Caesars Palace, Las Vegas, Nevada,

IEEE Catalog No. 82CH1759-0.
(2) E. B. Eichelberger and T. W. Williams, "A Logic Design

Structure For LSI Testability" 14th Design Automation

Conference Proceedings, pages 462-468, June 20, 21 and 22,

1977, New Orleans, Louisiana, IEEE Catalog No. 77CH1216-1C.

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