Browse Prior Art Database

FET Dottable Push/ Pull Driver

IP.com Disclosure Number: IPCOM000051032D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+4]

Abstract

The disclosed off-chip driver circuit receives input voltage levels of 0.5 V to 1.1 V and provides an output down level of 0.6 V at 16 mA, and an impedance equivalent to Rl at the up level (2.4V). This This up-level impedance allows other drivers dotted on the net to pull the output down; hence, this driver is "dottable". In addition, this driver transiently pulls the output to the up level (2.4 V) actively, and so it is also a push-pull driver. Conversion from active pull-up to passive (impedance equivalent to R1) occurs automatically via elements T2, R2, C1, and T4. The automatic nature of the impedance conversion eliminates the need for three-state drivers (with their associated logic overhead), where push-pull performance is necessary in a dotted environment.

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FET Dottable Push/ Pull Driver

The disclosed off-chip driver circuit receives input voltage levels of 0.5 V to
1.1 V and provides an output down level of 0.6 V at 16 mA, and an impedance equivalent to Rl at the up level (2.4V). This This up-level impedance allows other drivers dotted on the net to pull the output down; hence, this driver is "dottable". In addition, this driver transiently pulls the output to the up level (2.4 V) actively, and so it is also a push-pull driver. Conversion from active pull-up to passive (impedance equivalent to R1) occurs automatically via elements T2, R2, C1, and T4. The automatic nature of the impedance conversion eliminates the need for three-state drivers (with their associated logic overhead), where push-pull performance is necessary in a dotted environment.

Circuit Operation. When the input is high (1.1 V or above), T1 holds T5 off, T2 holds T4 off, and T3 is on, holding the output at a down level (0.6 V). When the input switches low (less than 0.5 V), T1 and T3 turn off, allowing T5 to pull the output high (actively). T2 is also off, but T4 cannot turn on until node 1 rises to VCC (approx. 20 ns, governed by R2 and C1. When node 1 rises sufficiently to turn on T4, T5 turns off and the output impedance is equivalent to R1 (neglecting the low impedance of T4).

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