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Hardware Assist for Microprocessor Implemented Main Frame

IP.com Disclosure Number: IPCOM000051080D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Dwyer, H: AUTHOR [+2]

Abstract

A hardware assist can significantly improve the performance of a microprocessor (MPU) having to interpret main frame instructions. It is intended that this particular task be significantly expedited by placing the main frame general purpose registers outboard to the MPU together with the instruction address register and an adder. This combination will enhance effective address generation with an MPU-implemented main frame system.

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Hardware Assist for Microprocessor Implemented Main Frame

A hardware assist can significantly improve the performance of a microprocessor (MPU) having to interpret main frame instructions. It is intended that this particular task be significantly expedited by placing the main frame general purpose registers outboard to the MPU together with the instruction address register and an adder. This combination will enhance effective address generation with an MPU-implemented main frame system.

For example, the MPU can load memory-mapped registers in the assist with the main frame instruction. See the figure for a schematic representation of this arrangement. The assist generates the effective address quickly compared to the speed with which the MPU alone would perform that task.

The generated address is left outboard to be available when the MPU needs it for a memory reference' Reading of the effective address is not necessary. When the MPU wants to use the effective address, it merely writes or reads with an address which "tells" the assist to present the effective address to the address bus. This technique and others of a similar nature are employed by this assist to improve overall system performance.

A listing of the assist terminology and table of some sample code therefore is depicted below. While intended to be applicable to 16-bit microprocessors, the assist arrangement described herein is usable with any MPU.

Term Remarks IAR1 Access Storage on external bus with Instruction Counter. Increment Instruction Counter by 2. Place incoming data

into OPREG.

IAR2 Same as IAR1, except data goes into OPER2.

IAR3 Same as IAR1, except-data goes into OPER1. IAR2 and IAR3 also initiate effective address generation within assist

hardware.

EFFADD1 The effective address generated from the OPER1 Register is used as the address for a storage reference.

EFFADD2 The effective address generated from the OPER2 Register (and OPREG (X2) when necessary) is used as the address

for a storage reference.

S370R1 The GPR specified by R1 in OPREG is addressed.

S37OR1...