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Short Channel Length Scheme to Reduce Poly 1 to 2 Shorts Using a Silicon Sidewall Oxidation Technology

IP.com Disclosure Number: IPCOM000051092D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Barbee, SG: AUTHOR [+2]

Abstract

The following scheme is proposed to eliminate in a double polysilicon technology the problem of thin first level polysilicon (poly 1) side walls which can cause poly 1/poly 2 shorts. The primary virtue of the technique is a very thick (/>/- 300 nm) sidewall oxide. A spin-off benefit is the reduction of the poly 1 device channel length by the sidewall oxide thickness. This compensates for the addition of a thin (5 to 10 nm) Si(3)N(4) layer in the poly 1 gate area.

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Short Channel Length Scheme to Reduce Poly 1 to 2 Shorts Using a Silicon Sidewall Oxidation Technology

The following scheme is proposed to eliminate in a double polysilicon technology the problem of thin first level polysilicon (poly 1) side walls which can cause poly 1/poly 2 shorts. The primary virtue of the technique is a very thick (/>/- 300 nm) sidewall oxide. A spin-off benefit is the reduction of the poly 1 device channel length by the sidewall oxide thickness. This compensates for the addition of a thin (5 to 10 nm) Si(3)N(4) layer in the poly 1 gate area.

A preferred process sequence is as follows:

1. Gate oxidation up to a SiO(2) layer 1 thickness of about

45 nm.

2. Deposition of a 5 to 10 nm thick Si(3)N(4) layer 2.

3. Deposition of poly 1 layer 3, POC1(3) doping, anneal, PSG

strip.

4. Deposition of a 10 nm Si(3)N(4) layer 4.

5. Definition of Si(3)N(4) and poly 1 layers 3 and 4,

respectively (standard photolithography and reactive

ion etching (RIE)).

6. Poly 1 sidewall oxidation to form SiO(2) regions 5 with a

(lateral) thickness of > 300 nm (high pressure oxidation may

be desired). Fig. 1 shows the structure at this stage.

7. RIE or hot H(3)PO(4) strip Si(3)N(4); etch SiO(2).

8. Gate oxidation up to a SiO(2) layer 6 thickness of about

65 nm using a >3:1 polysilicon:Si oxidation rate ratio.

9. Deposition of poly 2 layer 7, resulting in the structure of

Fig. 2. Further processing for shaping the poly 2 layer and

completing the desired device structures...