Browse Prior Art Database

Dynamic Selection of Partial Good Array Chips by Bit Address Selection

IP.com Disclosure Number: IPCOM000051103D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Bosch, LJ: AUTHOR [+2]

Abstract

A technique is disclosed for avoiding the sorting of memory chips in "partial good" applications and for allowing the intermixing on the same card of partial good chips having any section defective.

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Dynamic Selection of Partial Good Array Chips by Bit Address Selection

A technique is disclosed for avoiding the sorting of memory chips in "partial good" applications and for allowing the intermixing on the same card of partial good chips having any section defective.

Some arrays of modules require B bits on a single access where B equals 2/n/. If the modules are configured as either 64Kx9 or 32Kx18, for example, in an "all good" module, bits would be wasted due to the non-binary structure of the module organization. An obvious solution of not wasting bits would be to have an array configured in a binary structure, i.e., 64Kx8 or 32Kx16. These module organizations could be made available by the use of 8/9 partial good modules. However, an 8/9 partial good module would require characterization of 8 out of 9 good bits, and 9 substrates to implement the 9 possible ways of selecting 8 out of 9 things, as well as manpower and test set-up.

This technique utilizes 8/9 good modules without having to sort or characterize each chip.

Fig. 1 depicts a module that contains 8 chips. There are 20 column select (CS) signals that select a group of 4 chips within the module and 4 row select (RS) signals that select 4 groups of chip pairs within the module. Each chip within the module is organized as 8Kx9. A particular chip within the module is selected via column and row select bits. One of the 8K-9-bit bytes is selected by a 13-bit address field. This field has 8 bits to select...