Browse Prior Art Database

Bus Speed Adapter

IP.com Disclosure Number: IPCOM000051110D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR [+3]

Abstract

This article describes a bus speed adapter which enables a microprocessor with a single high speed bus architecture to be attached to a plurality of low speed I/O devices. The bus speed adapter comprises a pair of random-access memories (RAMs) which behave as a high speed I/O device when seen by the microprocessor and as a low speed microprocessor when seen by the I/O devices.

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Bus Speed Adapter

This article describes a bus speed adapter which enables a microprocessor with a single high speed bus architecture to be attached to a plurality of low speed I/O devices. The bus speed adapter comprises a pair of random-access memories (RAMs) which behave as a high speed I/O device when seen by the microprocessor and as a low speed microprocessor when seen by the I/O devices.

Referring to Fig. 1, microprocessor 10 is connected to random-access memory RAM M via a high speed data and addressing bidirectional bus 11. RAM M is coupled with random-access memory RAM F through high speed bidirectional bus 12. RAM F is connected to low speed bus 13 which is shared by N I/O devices, illustrated by I/O devices 1, 2 and N in the figure. RAM M is only accessed by microprocessor 10, while RAM F is only accessed by the I/O devices 1-N. When microprocessor 10 wants to send a message to a given I/O device, e.g., I/O device n, it writes this message at address N in RAM M. The message is then transferred to RAM F, and finally ~s sent through bus 13 to I/O device n. Any message sent by any I/O device to microprocessor 10 follows the reverse processing through RAM F and RAM M. Control logic 14 receives N interrupts, designated Interrupts 1-N from I/O devices1-N, respectively, and performs the following three tasks: I/O device addressing and I/O device-RAM F data exchange; data exchange between RAM M and RAM F; and handling global interrupt to microprocessor 10. Hereafter, we will assume the ...