Browse Prior Art Database

Hardware Register Duplicting a Local Store

IP.com Disclosure Number: IPCOM000051111D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Lechaczynski, M: AUTHOR [+4]

Abstract

This article describes a device allowing register to register instructions to be performed in a processor during one processor cycle, by using hardware registers which duplicate one of the group of registers in local store.

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Hardware Register Duplicting a Local Store

This article describes a device allowing register to register instructions to be performed in a processor during one processor cycle, by using hardware registers which duplicate one of the group of registers in local store.

Performing register to register instructions in a processor during just one processor cycle improves significantly its performance. However, these registers are located in a local store.

A register to register instruction implies a "read register A", "read register B", and "write target register" with the result of the operation. As a result, three read or write local store operations would be necessary. This is not possible in a conventional processor, due to the access time of the RAM (random-access memory) used as local store and to the single clocking design. Hardware registers duplicating the local store are used, which implies updating both local store and hardware registers. This updating scheme must allow the control program to find the correct value in the registers at any time and must not degrade processor performance.

This scheme is described below.

Two different register types have to be considered: the working register and the Instruction Address Register (IAR). Both types exist for any of the five program levels. Seven hardware working registers HWKR are implemented. They duplicate one of the five groups of seven registers LWKR in local store. They are used for performing a one cycle register to register instruction, as shown in Fig. 1.

At the end of the instruction, both target hardware work register HWKR and local store LWKR are updated. This is possible because just one local store write operation is performed during this cycle.

In case of interrupt, the current program level execution is stopped and the new program level starts to execute immediately at its program entry address. The hard...