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Memory Access Control for Multiprocessor System Using Microcode Bits to Transfer Memory Control on Idle Cycles

IP.com Disclosure Number: IPCOM000051124D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Temple, JL: AUTHOR

Abstract

In a multiprocessing system in which two processors A and B share main memory, control of memory rs transferred from one processor (e.g., A) to the other processor (B) when B has previously signaled a request for memory access and when microcode in A signifies that a sequence of memory accesses by A has been completed. The transfer signal is timed at a point in the memory cycle so that B can access memory at the completion of the last memory cycle in the sequence by A. The circuit is particularly useful with processors that are otherwise asynchronous.

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Memory Access Control for Multiprocessor System Using Microcode Bits to Transfer Memory Control on Idle Cycles

In a multiprocessing system in which two processors A and B share main memory, control of memory rs transferred from one processor (e.g., A) to the other processor (B) when B has previously signaled a request for memory access and when microcode in A signifies that a sequence of memory accesses by A has been completed. The transfer signal is timed at a point in the memory cycle so that B can access memory at the completion of the last memory cycle in the sequence by A. The circuit is particularly useful with processors that are otherwise asynchronous.

In some systems, the memory cycle time is equal to the processor cycle time. When the processor makes a sequence of accesses to memory, the processor and the memory operate in synchronism at their fastest possible rate. In a system of two processors that access the same memory, it is desirable to achieve this same synchronism when control of memory is transferred back and forth between the processors. However, in some systems the two processors operate asynchronously with independent clocks so that a delay may occur when the memory and a processor become synchronized.

The drawing shows the circuit for A and part of an identical circuit for B. When A has control of memory, latch 4a is set and the corresponding latch 4b is reset. A line 1b, "Release Memory to A" sets latch 4a when it is high, and it sets a la...