Browse Prior Art Database

Simultaneous Main Storage Access for a Multiprocessor

IP.com Disclosure Number: IPCOM000051148D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Cetina, MC: AUTHOR [+3]

Abstract

In a tightly coupled multiprocessing system, all processors, including the processing capability associated with the channels, share a common main storage. This single main storage may be implemented such that it is comprised of multiple, independently accessible, storage units. The communication between the processors and storage units might be via a common bus or multiple point to point connections, as shown in Figs. 1A and 1B, which each show a multiprocessor having four processors and two storage units. Each processor can be either a CPU or a channel processor. The common bus approach provides a less complex, less costly implementation but is limited to one data transfer at any one time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 3

Simultaneous Main Storage Access for a Multiprocessor

In a tightly coupled multiprocessing system, all processors, including the processing capability associated with the channels, share a common main storage. This single main storage may be implemented such that it is comprised of multiple, independently accessible, storage units. The communication between the processors and storage units might be via a common bus or multiple point to point connections, as shown in Figs. 1A and 1B, which each show a multiprocessor having four processors and two storage units. Each processor can be either a CPU or a channel processor. The common bus approach provides a less complex, less costly implementation but is limited to one data transfer at any one time. The multiple point-to-point design offers the opportunity for multiple simultaneous data transfers at the cost of additional hardware and increased complexity in maintaining integrity and synchronism between the processors. This article describes a mechanism that combines the cost advantages of a common bus with the performance benefits of multiple simultaneous transfer. By using two buses, up to two storage accesses may occur simultaneously. By limiting the number of simultaneous accesses in certain circumstances, redesign of the processors can be kept to a minimum.

A typical symmetric two-way multiprocessor is shown in Fig. 2. Note that there is a single path between the four processors and the two storage units such that only one data transfer can occur in any one machine cycle. The mechanisms insuring data integrity among the processors can take advantage of this sequencing of requests to main storage by implementing circuitry that need handle only one update to main storage per cycle. While there is only one logical path to storage, there may in fact be more than one physical path due to physical layout or to provide for partitioning of the system for operation flexibility or concurrent maintenance. If the additional physical paths can be exploited, at reasonable cost, the effective bandwidth to storage can be increased, reducing storage contention among the processors, thereby improving tightly coupled performance.

Fig. 3 shows how the machine of Fig. 2 was modified to exploit the existence of an additional physical path to storage. Two paths, one to each storage, had existed due to the symmetry of the configuration but had not been treated as independent paths. By modifying some control circuitry, two processors were permitted to access storage in the same machine cycle as long as they were accessing different storage units. (Note that all switches herein shown in simplified diagrammatic form are performed by well-known high-speed electronic gate circuits.)

To maximize the number of simultaneous storage accesses, the interleaving between the two storage units should be done using a low-order address bit, similar to the interleaving within a storage unit. But, if the interleaving betw...