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CMOS Static Random Access Memory Layout

IP.com Disclosure Number: IPCOM000051155D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Hiltebeitel, JA: AUTHOR

Abstract

A static random-access memory layout is provided in complementary metal oxide semiconductor (CMOS) technology with minimized cell area by sharing a diffusion well and contacts.

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CMOS Static Random Access Memory Layout

A static random-access memory layout is provided in complementary metal oxide semiconductor (CMOS) technology with minimized cell area by sharing a diffusion well and contacts.

The circuit diagram of a known CMOS static random-access memory cell which offers high performance, very low power and soft error rate immunity is illustrated in Fig. 1. The cell includes first and second cross-coupled N channel transistors N1 and N2, respectively, first and second P channel transistors P1 and P2, respectively, acting as loads and third and fourth N channel transistors N3 and N4, respectively, connected as input/output devices to a pair of bit/sense lines B0 and B1. The power supply terminal is indicated as VH.

The topology of two cells C1 and C2, of the type illustrated in Fig. 1, is shown in Fig. 2. Cell C1 includes transistors N1, N2, N3, N4, P1 and P2, bit/sense lines B0 and B1 and word line WL1, and Cell C2 includes transistors N1', N2', N3', N4', P1' and P2', bit/sense lines B0 and B1 and word line WL2. Cells C1 and C2 are formed in a P type silicon substrate which has an N type well 12, indicated by dashed lines, disposed therein. All N and P diffusions are formed in substrate 10, with polysilicon and metal lines being appropriately insulated except at the contacts. The N-P butted contact for power supply line VH is a contact which provides simultaneous contact to the P diffusions and to the N well, via an N+ diffusion.

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