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Regulated Power Supply for Large Memory Systems

IP.com Disclosure Number: IPCOM000051158D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR

Abstract

In a memory system having one thousand or more memory chips, an off-chip 8.5-volt power supply is eliminated by tying to an external or off-chip capacitor a small on-chip power supply circuit from each of the one thousand or more chips.

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Regulated Power Supply for Large Memory Systems

In a memory system having one thousand or more memory chips, an off-chip
8.5-volt power supply is eliminated by tying to an external or off-chip capacitor a small on-chip power supply circuit from each of the one thousand or more chips.

As indicated in the figure, a circuit including a terminal having regulated +5 volts applied thereto produces at a chip connection pad 10 a regulated voltage of
8.5 volts.

In operation, a 01 pulse is applied to transistors T1 and T3 to impress five volts across capacitor C1. A 02 pulse is then applied to transistor T2, with transistors T1 and T3 off, to produce a voltage of 5 volts on node A. At a high source to substrate potential, transistor T4, connected as a diode, typically has a
1.5 voltage drop from drain to source, thus generating at connection pad 10 a voltage of 8.5 volts. The connection pad 10 is connected to a relatively large off- chip capacitor C2.

Since one thousand or more memory chips, each having a pad 10 connected to capacitor C2, are in the system and only about 3 percent or fewer chips are active over a few-millisecond time average, current drain is light, and thus capacitor C1 can have a capacitance which is less than that of a single word line. Because capacitor C1 is small, transistors T1, T2, T3 and T4, which charge and discharge capacitor C1, can also be small. The on-chip circuit between the +5- volt terminal and the connection ad 10 may be sufficiently sma...