Browse Prior Art Database

Hardware Augmentation for Improved Performance of Communications Protocol Control

IP.com Disclosure Number: IPCOM000051167D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Cramer, CE: AUTHOR [+3]

Abstract

Commercially available OEM communications protocol controller chips are attachable to the using systems through direct memory access control. However, the real time programming requirements necessary to implement high speed data communication protocols often prevent functional use of the vendor chips at or near the actual rated speed of throughput. The system described below utilizes hardware logic circuits for performing some of the critical protocol functions intended to be performed by software in these OEM devices. A typical system is shown in the figure.

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Hardware Augmentation for Improved Performance of Communications Protocol Control

Commercially available OEM communications protocol controller chips are attachable to the using systems through direct memory access control. However, the real time programming requirements necessary to implement high speed data communication protocols often prevent functional use of the vendor chips at or near the actual rated speed of throughput. The system described below utilizes hardware logic circuits for performing some of the critical protocol functions intended to be performed by software in these OEM devices. A typical system is shown in the figure.

In the figure, the data flow path consists of a protocol controller 1, the hardware augmentation logic of the present disclosure 2, and a randomly addressable memory (RAM) 3, and microprocessor 4. Suitable busses interconnect these elements with the direct memory access (DMA) controller 5, which may be a commercially available OEM chip.

Protocol controller 1 receives or delivers data from or to a signal converter, such as a modem (not shown), and makes transfer requests to the DMA controller 5 on predetermined (e.g., bytes) boundaries. Controller 5 will make requests to the microprocessor system for control of the memory bus 6 and address bus 7. When control of these busses has been granted by the system processor 4, the controller 5 will transfer data from the memory 3 to the protocol controller 1 in transmit mode or from the protocol controller 1 to the memory in receive mode. Two controller channels are utilized in the DMA controller 5 for the receive function. One channel is used as a main buffer and the other is used as an alternate buffer. The augmentation logic 2 contains a counter which is maintained to keep track of the residual buffer space that remains. It is initially loaded by the program from the microprocessor 4 with the size in bytes of a buffer that is available and with the main or alternate buffer select bit. Also, there is a software settable latch for indicating that a buffer is clear. There is also logic which is used to detect a buffer overrun condition or an imminent overrun condition. Upon transfer of data from the direct memory access controller 5 to the memory 3, the buffer size counter which maintains the residual size of the buffer that remains is decremented appropriately to present the current remaining amount of buffer space. At the end of frame condition, the augmentation logic 2 performs a read operation on the protocol controller 1 to determine its status. Using a channel of the direct memory access controller 5, the augmentation logic 2 then writes it into the status buffer area in memory 3 the status of the protocol controller 1. This is followed by two bytes of status information generated by the augmentation logic 2 consisting of the residual buffer count indicating the amount of space left in the residual buffer and the interrupt status. Augmentation logic...