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Simultaneous Storage of Two Asynchronous Memories for CRT Refresh

IP.com Disclosure Number: IPCOM000051171D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Hurst, JP: AUTHOR [+3]

Abstract

The controller for this work station is divided into two major logic groups. The base logic consists of an Intel 8085 serving as the work station controlling microprocessor, an Intel 8041 as the interface controller used for host communication, an Intel 8257 DMA (direct memory access) controller, 19K bytes of memory, 3K of which is random-access memory (RAM) and miscellaneous support logic. The display logic consists of the CRT control logic, RAM, ROS (read-only storage), and associated interface logic.

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Simultaneous Storage of Two Asynchronous Memories for CRT Refresh

The controller for this work station is divided into two major logic groups. The base logic consists of an Intel 8085 serving as the work station controlling microprocessor, an Intel 8041 as the interface controller used for host communication, an Intel 8257 DMA (direct memory access) controller, 19K bytes of memory, 3K of which is random-access memory (RAM) and miscellaneous support logic. The display logic consists of the CRT control logic, RAM, ROS (read-only storage), and associated interface logic.

The 8085 has no knowledge of the memory on the display side of the logic. The regenerative (regen) memory on the base side and the CRT refresh RAM on the display side, run asynchronously to each other with the refresh RAM being accessed 50% of the time for refreshing the display. Data written into the CRT regen RAM (2K bytes) is simultaneously stored in the CRT refresh RAM (2K bytes) independently of any processor or DMA interaction. Since this transfer is done in hardware, no additional microcode support or processing time is needed for CRT refresh.

Whenever the regen area of memory is written to, the address being accessed and the data being sent are trapped and latched in the data and address latches in the display logic. In this interface, data is translated via a 36K-bit data translate ROS to accommodate a multinational character generator. The address is also translated to accommodate the diff...