Browse Prior Art Database

Multiprocessor Synchronization Decision Method

IP.com Disclosure Number: IPCOM000051183D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Strong, HR: AUTHOR

Abstract

This invention relates to a process whereby a collection of processors can determine simultaneously whether any of them is in a specified state. This process does require weak synchronization since all must agree simultaneously to enter the decision process. At the end of the process they will all have agreed on their current mutual status.

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Multiprocessor Synchronization Decision Method

This invention relates to a process whereby a collection of processors can determine simultaneously whether any of them is in a specified state. This process does require weak synchronization since all must agree simultaneously to enter the decision process. At the end of the process they will all have agreed on their current mutual status.

An external n-way comparison communication device replaces presumably slower communication via messages among the processors. There is no explicit contention for the device and no message formatting required. The device has its own clock and repeatedly goes through a cycle of reading the most recently sent signals from the processors and then comparing these signals and sending to each processor an indication of whether its most recently sent signal was the minimum of all most recently sent signals.

One specific signal is designated the id signal and translated by the device into n distinct signals corresponding to the n ports of the device, a different id being received for each port. Also, a specific subset of the signals is designated as reset to zero signals. When a reset to zero signal is the most recently received, and during a cycle it is determined to be the minimum, then at the conclusion of that cycle it is reset to zero so that the device operates as if zero were the most recently sent signal for subsequent cycles.

Illustratively, let the integers 0 through 7 denote eight specific signals with the usual order, let 1 be the id sig...