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Josephson Memory with one Junction Cells

IP.com Disclosure Number: IPCOM000051185D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Wolf, PH: AUTHOR

Abstract

A Josephson memory is proposed in which each storage cell in the array comprises only a single Josephson device and an ohmic or a non-linear resistor in series therewith. By proper application of bias, read, and write, voltages non-destructive read-out operations are feasible.

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Josephson Memory with one Junction Cells

A Josephson memory is proposed in which each storage cell in the array comprises only a single Josephson device and an ohmic or a non-linear resistor in series therewith. By proper application of bias, read, and write, voltages non- destructive read-out operations are feasible.

The memory cell is based on the bistability of Josephson tunnel junctions with binary values "0" and "1" corresponding to the Josephson or no voltage and to the voltage state, respectively. Fig. 1 is a sketch of the array, only one cell and one set of x- and y-lines being shown. The cell consists of a junction J and a biasing resistor R which can be ohmic as well as non-linear. The x- and y-lines are connected to voltage sources Y(x), Y(y), providing for bias, write and read currents. For reading, a current sensor S is provided.

The memory operation is illustrated in Fig. 2 which represents the I/V characteristic of the proposed cell. It also shows the load line of ohmic resistor
R.

Storage State: Voltage V(B) is applied to the cells so that a stable bias is guaranteed for both the no-voltage and the voltage state, the first being defined as "0", the second as "1". The voltage V(B) at the cell can be achieved by choosing, e.g., V(y)=0.5 V(B) and V(x)=0.5 V(B) for all x- and y-lines.

Write Operation: The x- and y-lines of the fully selected cell are pulsed to voltage values as follows:

Write "0": The cell voltage is reduced to V(/WRO) so that

only the no=voltage state exists. For instance, V(WRO)=0 can

be achieved by choosing V(x)=V(y)=0. If the bias voltage V(B)

is switched on again the junction stays in the no-voltage

state. Half-selected cells supplied with a voltage of 0.5

V(B). They remain in their "0" or "1" state provided 0.5

V(B) less than V(r), V(r) being the voltage bel...