Browse Prior Art Database

Read Only Bypass of Cache

IP.com Disclosure Number: IPCOM000051192D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Duke, AH: AUTHOR [+4]

Abstract

A user is attached to a storage hierarchy having a volatile cache and a retentive backing store. Normally, reading and writing by the user is directed to the volatile cache to the exclusion of the backing store. Under certain circumstances, it is advantageous for the user to directly access the backing store to the exclusion of the volatile cache. For purposes of data integrity, for the data stored in the volatile cache, the bypassing of the cache is limited to only reading data from the backing store to the user. In this manner, all data written to the system flows through the volatile cache.

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Read Only Bypass of Cache

A user is attached to a storage hierarchy having a volatile cache and a retentive backing store. Normally, reading and writing by the user is directed to the volatile cache to the exclusion of the backing store. Under certain circumstances, it is advantageous for the user to directly access the backing store to the exclusion of the volatile cache. For purposes of data integrity, for the data stored in the volatile cache, the bypassing of the cache is limited to only reading data from the backing store to the user. In this manner, all data written to the system flows through the volatile cache.

A pair of switches S1 and 52 represent a memory controller which switches the write data W to the volatile cache and switches the read data from the volatile cache or from the backing store to the user. When switch S2 is set to the backing store's position B, only data in the backing store is read to the user. Switch S1 is also set to the B position which permits no writing of data by the user to the storage system. The normal stage/destage data transfers between the volatile cache and the backing store are performed independent of the switches S1 and S2, as indicated by the double-headed arrow RW. In a peripheral data storage system, the illustrated read-only cache bypass applies to each individual addressable data storage device. For example, when the backing store is a plurality of direct-access storage devices, any one or all of the backing sto...