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Programmable Routing of Interrupts in a Multiprocessor Network

IP.com Disclosure Number: IPCOM000051197D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Hennet, PP: AUTHOR [+4]

Abstract

A method to select under program control the routing of interrupts in a multiprocessor network (a network of individual processors in a single processing system) is described below. Using this method, one interrupt request can be routed to any set of the processors in a multiprocessor network, and the set of recipients of that interrupt is under program control.

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Programmable Routing of Interrupts in a Multiprocessor Network

A method to select under program control the routing of interrupts in a multiprocessor network (a network of individual processors in a single processing system) is described below. Using this method, one interrupt request can be routed to any set of the processors in a multiprocessor network, and the set of recipients of that interrupt is under program control.

The processors in many multiprocessor networks communicate using interrupts. One processor may issue an interrupt request to another, thereby the one processor alerts the other to the existence of some condition. Likewise, interrupt requests from external sources are used to alert processors to the occurrence of events exterior to all processors.

In a multiprocessor network as herein set forth, it is proposed that a register be associated with each type of interrupt, that the register be readable and writable by programs executing in processors in the network, that each processor permanently correspond to a unique bit in the register, and that the delivery of any interrupt request of one type to a processor will be dependent upon the status of the corresponding bit in the register for that interrupt type. For example, a bit value of ONE in a register could indicate that any interrupt request of the type of that register is to be delivered to processors corresponding to that bit, while a bit value of ZERO would block delivery of the interrupt r...