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Using A1(2)0(3) for VLSI Multilevel Interconnections

IP.com Disclosure Number: IPCOM000051201D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Ting, CY: AUTHOR

Abstract

This article relates generally to the fabrication of semiconductor devices and more particularly to a process for achieving high density and multilevel interconnections for VLSI (very large-scale integration) applications.

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Using A1(2)0(3) for VLSI Multilevel Interconnections

This article relates generally to the fabrication of semiconductor devices and more particularly to a process for achieving high density and multilevel interconnections for VLSI (very large-scale integration) applications.

As VLSI technology advances, Jevice and circuitry density will be more and more limited by the thin film interconnection technology, particularly in the area of sub-micron devices.

High density (small line width and spacing) and multilevel (more than 3) interconnections are urgently needed to ease the limitations. This article describes a new structure and a new technology to achieve this goal.

The process for achieving multilevel connection is as follows:

In Fig. 1, a silicon substrate covered with SiO(2) is shown after contact hole and contact metallurgy preparation. The first level metal (A1-Cu or W) ay be delineated by either lift-off or reactive Lon etching (RIE).

Fig. 2 shows an intermediate stage in the fabrication of the desired structure after deposition of a thin layer of A1(2)0(3) (about 500 Angstrom or less at a temperature less than 400 degrees C) by plasma enhanced chemical vapor deposition (CVD) or by physical sputter deposition. After A1(2)0(3) deposition, a layer of SiO(2) or Si(3)N(4) or other material which can be etched by CF plasma is deposited at a temperature of about 400 degrees C using sputter deposition or plasma CVD.

Using conventional photolithographic and etching techniques, a mask for a via hole is provided. Using RIE, the SiO(2) or Si(3)N(4) is etched in CF(4) (or CF(4)+0(2)) plasma to open the via hole. The A1(2)0(3) is used as an end etch stopper.

Referring now to Fig. 3,...