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Device Structure and Fabrication Process for a Fundamental Mode Acoustical

IP.com Disclosure Number: IPCOM000051209D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 41K

Publishing Venue

IBM

Related People

Brady, MJ: AUTHOR [+3]

Abstract

This article describes a device structure and a process for making it. This device is a highly accurate, fast clock (i.e., a fundamental mode piezoelectric oscillator) that may be grown on a silicon or gallium arsenide wafer. The procedures and equipment needed to fabricate it are those usually used in the fabrication of integrated circuits.

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Device Structure and Fabrication Process for a Fundamental Mode Acoustical

This article describes a device structure and a process for making it. This device is a highly accurate, fast clock (i.e., a fundamental mode piezoelectric oscillator) that may be grown on a silicon or gallium arsenide wafer. The procedures and equipment needed to fabricate it are those usually used in the fabrication of integrated circuits.

The current method of making a fundamental mode acoustical oscillator is to deposit a piezoelectric material with metal electrodes on either side of it onto a thin membrane etched into a silicon wafer. In order to operate at the fundamental mode the total thickness of the structure must be one-half the accoustical wavelength. For a ZnO transducer operating at 300 MHz, this corresponds to a total physical thickness of about 15,000 nm.

Fig. 1 shows one embodiment of a fundamental mode acoustical oscillator that is in use today. Item 1 is the piezoelectric material, such as ZnO. Items 2 and 3 form the top electrode and are usually Ti and Au, respectively. They are usually delineated using lift-off techniques. Items 4, 5 and 6 form the base electrode and are usually Ti, Au and Ti, respectively. These are also used as the seed layer for the growth of the piezoelectric material. Item 7 is a (100) silicon wafer approximately .25 mm thick. Item 8 is a heavily doped p(+) region (usually obtained by diffusion) that is required to stop the etching in forming the membrane 9. Item 10 is a region of the base electrode that is exposed for making electrical contact to this electrode. Item 10 is not needed if a metal such as A1, Item 11, is deposited onto the bottom of the membrane. If item 10 is used for electrical contact, then item 11 is not required.

The approximate thicknesses of the various layers are listed below.

Item Material Thickness (nm)

1 ZnO 13,000

2 Ti 20

3 Au 100

4 Ti 20

5 Au 100

6 Ti 20

9 p+ Si 1000 - 3000

11 A1 1000.

The device described above and the process for making it have several inherent problems. These are summarized below.

The heavily doped p+ layer in the silicon, which is required as an etch stop, usually has a large number of defects such as dislocations. This results in Si surfaces that are not flat. These defects cause spatial variations in the physical properties of the piezoelectric material Which decreases the Q of the resonant circuit.

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The thickness of the p(+) layer is hard to control accurately. This results in a spread (from wafer to wafer) in the resonant frequency of the oscillator.

Silicon wafers with thin membranes, especially large area membranes, are very fragile. Cleaning, processing, and handling reduce the yield of the manufacturing process. Because the membranes are so fragile, the deposition processes cannot always be optimized.

The membranes have a much lower thermal conductivity than the thicker silicon wafers. During some processing steps the membranes can get hot. The h...