Browse Prior Art Database

Performance Enhanced Scheme for CMOS Circuits

IP.com Disclosure Number: IPCOM000051211D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 24K

Publishing Venue

IBM

Related People

Dennard, RH: AUTHOR [+3]

Abstract

This article describes a technique to improve the performance or chip density of CMOS circuits without raising the power supply V(DD). The current-carrying capability of an FET is determined by the term V(GS)-V(T), the principle of the present technique is to allow the V(T) of either (or both of the p- and n- channel FETs in CMOS circuits, i.e., to change the operation mode of the device from enhancement toward depletion such that the term V(GS)-V(T) becomes larger.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Performance Enhanced Scheme for CMOS Circuits

This article describes a technique to improve the performance or chip density of CMOS circuits without raising the power supply V(DD). The current- carrying capability of an FET is determined by the term V(GS)-V(T), the principle of the present technique is to allow the V(T) of either (or both of the p- and n- channel FETs in CMOS circuits, i.e., to change the operation mode of the device from enhancement toward depletion such that the term V(GS)-V(T) becomes larger.

It is well known that conventional CMOS circuits dissipate an extremely small amount of standby power but sometimes suffer from the penalty of having longer propagation delay and being less dense when being compared with other techniques such as NMOS or MTL (merged transistor logic). CMOS will certainly become more attractive and versatile if power is traded for better performance or chip density. The present technique provides such trade-off between power and performance (or chip density). According to this technique, if either (or both) of the p and n- channel devices is made depletion type, a static "on-current" will increase the standby power but the V(GS)-V(T) gate voltage of the OH device in an inverter becomes even larger, further improving the performance. To an extent, this type of circuit looks like an HMOS inverter with p-type depletion load or a PMOS inverter with an n-type depletion load. However, because both n- and p-type devices still switch between a more conductive state and a less conductive state according to the input signal, the standby on-current will be much smaller than that of a true depletion load with a passive input.

The figure shows a simple CMOS inverter with a capacitive load. Ordinarily, both p- and n-channel devices are of the enhancement type. They actively pull up or pull down the output node with a current which can roughly be expressed in its initial state as I(DS)=1/2 (V(GS)-V(T))/2/ Gamma W/L

During the pull-up cycle, assuming that F(DD)-2V, V(in)-0V and V(T)=-0,5V, then I(DS)=1/2 (-2+0.5)/2/ Gamma W/L

equals -1.1...