Browse Prior Art Database

Operable Soliton PLA System

IP.com Disclosure Number: IPCOM000051217D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 27K

Publishing Venue

IBM

Related People

Faris, SM: AUTHOR

Abstract

This article relates generally to superconducting logic circuits and more particularly to Josephson soliton logic circuits in the programmable logic array environment.

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Operable Soliton PLA System

This article relates generally to superconducting logic circuits and more particularly to Josephson soliton logic circuits in the programmable logic array environment.

A number of soliton and read-only memory circuits are shown in (1). In particular, Figs. 4A and 6A show a soliton NOR circuit and a ROM array, respectively. By using the NOR circuit of Fig. 4A in Fig. 6A, a NOR array can be formed. By utilizing a NOR array as described in (1), a soliton programmable logic array (PLA) using inverting and noninverting interfaces, as shown in the above figure, may be fabricated.

Referring now to the figure, here, a NOR soliton array 10 has the signals A,B,...,Z and their complements applied to its inputs, producing at its outputs the signals f(1)=A + B +.....Z; f(2)=A + B +.....Z; f(n)=A + B +.....Z.

Using DeMorgan's theorem, these become: f(1)=A + B.....Z; f(2)=A.B.....Z; .....; f(n)=A.B.....Z.

Thus one obtains AND function from the NOR array 10. Now f(1), f(2).

Thus one obtains AND function from the NOR array 10. Now f(1), f(2)...f(n) drive a noninverting interface 11, which in turn drives soliton NOR array 12. Noninverting interface 11 may be a plurality of Josephson junctions, the current through each of which is switched or not switched to an output circuit when there is an output or no output, respectively, on each of the outputs of NOR array 10. The resulting current or no current on the output lines acts as input to NOR array 12.

Th...