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I/O Pin Assignment in a Computer

IP.com Disclosure Number: IPCOM000051219D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 63K

Publishing Venue

IBM

Related People

Donath, WE: AUTHOR

Abstract

Current automatic design procedures for assigning I/O pins of chips higher level packages ignore the performance of the system. In some of these earlier techniques, every change on the system required that the effects of the change be propagated. This article describes a method for pin assignment which does not require propagation for every assignment and which considers the performance of the system in making the pin assignment. It is based upon two timing analysis runs, one for giving a preliminary estimate of the criticality of the nets, and the second run for verifying that performance was indeed optimized.

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I/O Pin Assignment in a Computer

Current automatic design procedures for assigning I/O pins of chips higher level packages ignore the performance of the system. In some of these earlier techniques, every change on the system required that the effects of the change be propagated. This article describes a method for pin assignment which does not require propagation for every assignment and which considers the performance of the system in making the pin assignment. It is based upon two timing analysis runs, one for giving a preliminary estimate of the criticality of the nets, and the second run for verifying that performance was indeed optimized.

The physical structure of a computer is hierarchical. That is, circuits (gates) are contained in chips which are mounted on a multichip carrier, which is again mounted on the next higher level package (for example, a board), etc. Each package (chip, card, board, etc.) is provided with I/O pins for communication to the next higher level of package. Connection is established between the pins of the various devices residing on it, as well as its own I/O pins. These pins are assigned to the various nets, which require communication across the various interfaces. Some of these nets tend to be critical in the sense that, should their delay exceed the minimum possible, then system delay will be increased.

The goal of the method herein is to give critical nets the best possible pin assignments, and to allow other nets to take what they can get. It is assumed that placement of chips and modules is complete. Timing analysis is used to classify the nets in terms of their "slack", where slack measures how much longer the delay over a particular net can be and still not impact system performance. A preliminary timing analysis run is made where each net is assumed to have its optimum pin assignment regardless of whether this conflicts with other nets. The nets are then sorted in order of increasing slack, and a second pin assignment is made for the pins in each net. In this case, when a net uses a pin, the pin is removed from further use in other nets. The pin assignment is made for the nets in order for increasing slack, so the most critical nets get first pick of the pins.

A second timing analysis run measures the effectiveness of the method; that is, if the worse case slack is not significantly worse than the worst-case slack in the first timing analysis run, then the assignment is highly effective. Net Optimization

Assume that each net consists of a source and a set of sinks (where multiple sources exist in a net, such as when sources are dot-ORed or dot-ANDed. These sources are usually required to be placed close together and can be treated as a single source). The sinks may be separated from the source by many boundaries, such as chip boundaries, module boundaries, etc. Fig. 1 gives a representation of such a net (here, the net is distributed over 4 chips and 2 modules), and Fig. 2 gives a diagramma...