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Directly Addressable Register Stack Area

IP.com Disclosure Number: IPCOM000051221D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Rechtschaffen, RN: AUTHOR [+2]

Abstract

A stack of register contents and embedded stack pointers is used to avoid decoder delay associated with Address Generate Interlock in the following manner: When a general purpose register (GPR) is loaded, a stack pointer (Beta(1)) is associated with the GPR. The stack pointer and the contents loading are either taken from another stack or from another source (such as main memory or PSW (Program Storage Word)). In the latter case, associated stack entries are updated with the newly assigned pointer so that subsequent retracing of the code utilizes this stack directly. The number of stacks and associated pointers are not limited to 16, as is generally the case. The size of the data entry within the stack is the cache accesss (DW, QW). Address generation involving indexing has not been considered.

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Directly Addressable Register Stack Area

A stack of register contents and embedded stack pointers is used to avoid decoder delay associated with Address Generate Interlock in the following manner: When a general purpose register (GPR) is loaded, a stack pointer (Beta(1)) is associated with the GPR. The stack pointer and the contents loading are either taken from another stack or from another source (such as main memory or PSW (Program Storage Word)). In the latter case, associated stack entries are updated with the newly assigned pointer so that subsequent retracing of the code utilizes this stack directly. The number of stacks and associated pointers are not limited to 16, as is generally the case. The size of the data entry within the stack is the cache accesss (DW, QW). Address generation involving indexing has not been considered.

A stack of locations and their contents can be used to avoid decoder delay because a memory access is required between the setting and use of a GPR. Consider the following sequence:

Alpha: L R1, D1 (0,R10)

Alpha+1: L R2; D2 (0,R1)

Alpha+2: TM 'M',D3 (0,R2).

Under normal conditions a memory (cache) access is required between instructions Alpha and Alpha+1 and also between Alpha+1 and Alpha+2. Decoding and Address Generation can not occur within the same cycle or on successive cycles.

If this sequence is re-executed with the possible exception that D3 is different, a stack of reuseable register contents can be accessed to avoid the ca...