Browse Prior Art Database

Overlapping Address Generate Delay

IP.com Disclosure Number: IPCOM000051226D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+3]

Abstract

The performance of pipelined processors can be enhanced if delays associated with the decoder, such as Address Generate Interlock and Branch Target Fetch, can be overlapped.

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Overlapping Address Generate Delay

The performance of pipelined processors can be enhanced if delays associated with the decoder, such as Address Generate Interlock and Branch Target Fetch, can be overlapped.

Current highly pipelined processors will stop decoding when one of several delays occur. A principal delay in the decoder is the Address Generate Interlock (AGI). Simulations have shown that the elimination of Address Generate Interlock enhances the overlap of other delays, such as those associated with Taken Branches. This implies that if the decoder were to continue "processing" instructions looking for the next delay-inducing instruction, that subsequent delay could be overlapped with the actual decoding of the subsequent instructions. The examination of instruction sequences has indicated that the occurrence of an AGI and an unrelated TAKEN BRANCH is sufficiently high so that a considerable portion of the TAKEN BRANCH delay would be overlapped. The main advantage is that the decoder is unused during the delay, and so the hardware impact of continued decoding is thereby reduced.

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