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Mechanism to Overlap Decoder Delay with Long OPS

IP.com Disclosure Number: IPCOM000051229D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+3]

Abstract

The overlap of decoder delay in the categories of Taken Branch and Address Generate Interlock susceptible to Load Bypass is accomplished via the following mechanism.

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Mechanism to Overlap Decoder Delay with Long OPS

The overlap of decoder delay in the categories of Taken Branch and Address Generate Interlock susceptible to Load Bypass is accomplished via the following mechanism.

Current highly pipelined processors will stop decoding during the processing of a multi-cycle E-unit operation (LONGOP) since the Instruction Queue will fill or "ALL OARS (Operand Address Registers) BUSY" will be raised. The decoder can continue to "process" instructions during these idle cycles in the hope of finding the "next delay" which it can resolve directly. This delay, such as a LOAD-induced Address Generate Interlock or a TAKEN BRANCH TARGET fetch, if unrelated to the LONG OP, can be overlapped with: the intervening instruction processing, or (if the LONG OPS will allow or will permit an intervening cache access) with the Long Op itself. The hardware implementation of this look-ahead to the next delay is reduced by the observation that the decoder which is used to do this look-ahead is currently unused during the delay.

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