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Memory Address Relocation Using Full Adder

IP.com Disclosure Number: IPCOM000051240D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Adair, JG: AUTHOR [+2]

Abstract

A full adder is used in a subtractive mode for translating a system memory address into a card memory address in a system in which the memory card control logic always responds from address zero to the memory size of the card.

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Memory Address Relocation Using Full Adder

A full adder is used in a subtractive mode for translating a system memory address into a card memory address in a system in which the memory card control logic always responds from address zero to the memory size of the card.

The full adder shown in Figs. 1 and 2 is used in a subtractive mode by adding the inverse of the subtrahend plus one to the minuend. In Fig. 1, the A inputs represent the minuend and are connected to the high-order bits of the system address bus. The B inputs represent the subtrahend and control the address relocation. The Carry input is tied to a logical one. The Sum outputs are the modified high order address bits to the memory card address control logic so that the beginning memory address on the card is at zero.

The size of the adder and the number of the high order address bits used depend on the size of the memory increments and the number of memory increments used. A(S) is the address bit corresponding to the size of the memory increments. A(S+X) is the address bit corresponding to the highest address bit used in the adder. The size of the adder used is X+1 bits. The number of memory increments is 2/(X+1)/. For a memory card address translation beginning with zero on the memory card, the B inputs are set to the inverse of the desired system starting address on the A inputs.

Fig. 2 shows a circuit for a total memory size of 16 increments of 32K bytes each. The B inputs are controlled by jumpe...