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Exact Interrupt Capability for Processors Using a Packet Switching Storage Channel

IP.com Disclosure Number: IPCOM000051242D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Hester, PD: AUTHOR [+3]

Abstract

This article describes a technique for providing "exact interrupts" in the address translate or storage protect mode for a high-speed microprocessor which employs pipelining and a packet-switching main storage channel. "Exact interrupt" means that sufficient information concerning the processor state can be saved, the interrupt serviced, and the previous state restored so that the interrupt is invisible to the program that was interrupted.

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Exact Interrupt Capability for Processors Using a Packet Switching Storage Channel

This article describes a technique for providing "exact interrupts" in the address translate or storage protect mode for a high-speed microprocessor which employs pipelining and a packet-switching main storage channel. "Exact interrupt" means that sufficient information concerning the processor state can be saved, the interrupt serviced, and the previous state restored so that the interrupt is invisible to the program that was interrupted.

In the normal mode of operation, the processor prefetches instructions from storage and sends them to an internal buffer from which the instructions are subsequently executed. When an instruction is executed which requires data to be fetched from storage, a read command is generated for the required data and sent to a buffer which transmits the request to storage via the storage channel. While this fetch is occurring, subsequent instructions are executed, provided they do not reference the data which has not yet been loaded from storage. Thus, the storage access time for the data is not apparent to the processor. If any instruction in the prefetch buffer is executed which references the data before it returns from storage, the processor enters an idle state until the data returns. Certain hardware (logic gates) is required to enable the processor to function in the manner described above. This hardware consists of comparators to detect whether the instruction currently being executed is referencing a register which is waiting to be loaded with data from storage, and some logic in the control section to temporarily suspend processor activity until the data is loaded.

The solution to providing exact interrupts when operating in storage protect or address translate mode makes use of the existing hardware described above. When an instruction which references storage data is executed, the control logic immediately places the processor in the idle condition, and no more instructions can be executed until the requested data returns. Along with the requested data comes a control signal called "EXCEPTION". If "EXCEPTION" is inactive when the data returns, the read operation is successful, the data is placed in the appropriate register, and execution of the next instruction begins. However, if "EXCEPTION" is active when data returns, the data is not written into any register, but an interrupt is generated instead. Storage write operatio...