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Dynamically Reconfigurable Vectors

IP.com Disclosure Number: IPCOM000051271D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 40K

Publishing Venue

IBM

Related People

Huang, JW: AUTHOR [+3]

Abstract

This article describes an approach to vector processing using a register set. The operands to be used in an instruction are defined by a bit map on the register set. These bit maps (several sets) can be created explicitly, or they can be the result of multiple condition code results from previous vector operations. The use of bit maps provides the ability to selectively execute elements within the register set to minimize non-productive operations.

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Dynamically Reconfigurable Vectors

This article describes an approach to vector processing using a register set. The operands to be used in an instruction are defined by a bit map on the register set. These bit maps (several sets) can be created explicitly, or they can be the result of multiple condition code results from previous vector operations. The use of bit maps provides the ability to selectively execute elements within the register set to minimize non-productive operations.

An organization with the capability of defining and dynamically reconfigurating logical vectors is presented. In comparison to the IBM System/370, the number of addressable general purpose and floating point registers is greatly expanded. The floating point registers will double as decimal registers, thus providing the opportunity to have decimal register-to-register operations. A set of mask registers is provided both to select the fixed, floating, or decimal registers that will participate in an operation and to be used directly for bit manipulation. The above-described registers can be thought of as the 'data' register set, whereas the registers that are used to define which 'data' registers will be used in an operation and how they will be used can be thought of as 'specification' registers. A list of the two sets of registers and a schematic of the organization is presented. A description of each register will then be provided along with some discussion of its use.

The register sets, comprised of both 'data' and 'specification' registers, consist of: 2048 General Scalar Registers (GSR), 32 bits each

2048 Floating Point/Decimal Scalar Registers (F/DSR),

64 bits each

16 Mask Register (MR) sets of 2048 scalar elements,

1 bit each

1 Condition Code Register (CCR) of 2048 elements,

3 bits each

16 Vector Origin Registers (VOR), 16 bits each

16 Physical Length Registers (PLR), 16 bits each

16 Element Participation Registers (EPR), 16 bits

each

16 Current operand Pointer Registers (COPR), 16 bits each

16 Stride Registers (STR), 32 bits each

16 Indirect Registers (IR), 4 bits each

Optional Registers 8 Extended Count Registers (ECR), 64 bits each

16 Extended Count Pointers (ECP), 8 bits each.

Description of the Registers: General Scalar Registers - These registers have the same function as the System/370 general-purpose registers. They can be used for fixed-point or logical operations and as base or index registers for address arithmetic. The registers are addressable individually as 0-2047.

Floating Point/Decimal Scalar Registers - These registers have the same function as the System/370 floating point registers. They can be used as System/370 compatible in floating-point arithmetic. The registers can also be

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loaded with packed format data for a new set of decimal register-to-register instructions. The data in the registers is logically floating point or packed decimal based on the instruction that uses the register. These registers are also a...