Browse Prior Art Database

Dynamic First Stage for a Shift Register

IP.com Disclosure Number: IPCOM000051298D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Moore, VS: AUTHOR [+2]

Abstract

A dynamic register stage is described that may be used as an L1 latch i a Level Sensitive Scan Design (LSSD) compatible system, such as that described in U. S. Patent 3,783,254, or as a clock stage in any shift register.

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Dynamic First Stage for a Shift Register

A dynamic register stage is described that may be used as an L1 latch i a Level Sensitive Scan Design (LSSD) compatible system, such as that described in U. S. Patent 3,783,254, or as a clock stage in any shift register.

Reduction in power usage is realized due to the elimination of DC circuitry normally utilized in an LSSD chain on an LSSD-compatible chip. There is zero power dissipation except during use.

As shown in the drawing, the circuit includes a number of field-effect transistors T1-T7 all of which are the "enhancement" type except for T4 which is a "depletion" type. The clock 1 signal activates the inverter comprising transistors T2 and T3, and the datum is stored on capacitor CS which is the gate capacitance for transistor T6. The clock 2 signal validates the output datum and also discharges the gate of transistor T3 to maintain data integrity on capacitor CS.

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