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Read Only Storage Patch Hardware for Interrupt Driven Microprocessors

IP.com Disclosure Number: IPCOM000051302D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Eggebrecht, LC: AUTHOR

Abstract

The figure shows a simple read-only storage (ROS) patching technique. By way of example, an Intel 8085 is considered to be microprocessor (MPU) 10, although it should be noted that any microprocessor with a similar architecture including an interrupt input can be used. The patch hardware 12 circuit is added to the microprocessor 10 bus structure in the manner shown by the figure. The patch hardware generates a hardware interrupt to the RST 7.5 interrupt input of microprocessor 10 whenever an instruction operation code read occurs within a tagged 16 byte boundary. Such an operation code read is controlled by the S0, S1 and RD signals from microprocessor 10 applied to enable AND gate 14 and flip-flop 16 to generate the interrupt.

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Read Only Storage Patch Hardware for Interrupt Driven Microprocessors

The figure shows a simple read-only storage (ROS) patching technique. By way of example, an Intel 8085 is considered to be microprocessor (MPU) 10, although it should be noted that any microprocessor with a similar architecture including an interrupt input can be used. The patch hardware 12 circuit is added to the microprocessor 10 bus structure in the manner shown by the figure. The patch hardware generates a hardware interrupt to the RST 7.5 interrupt input of microprocessor 10 whenever an instruction operation code read occurs within a tagged 16 byte boundary. Such an operation code read is controlled by the S0, S1 and RD signals from microprocessor 10 applied to enable AND gate 14 and flip-flop 16 to generate the interrupt.

The tagged patch area information is stored in a 4K X 1 static random-access memory (RAM) 18. By using different size random-access memory modules and shifting the address field inputs to the module, different patch size blocks can be selected. To tag a block as requiring a patch, the DO bit is written into memory
18. When the program attempts to execute an instruction in a tagged block, the DO output from memory 18 is applied through AND gate 14 to enable flip-flop 16 to generate an interrupt to the system.

In operation, a read-only storage patch program which may be included in a read-only storage module 20, or which may be loaded from a magnetic media, such as a diske...