Browse Prior Art Database

High Speed, Low Volume Data Array Self Test

IP.com Disclosure Number: IPCOM000051321D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Williams, TW: AUTHOR

Abstract

U.S. Patent 3,961,252 shows a circuit for testing an embedded array by using pseudo-random generators (PRGs) of the shift register type for cycling the addresses and data pseudo-randomly.

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High Speed, Low Volume Data Array Self Test

U.S. Patent 3,961,252 shows a circuit for testing an embedded array by using pseudo-random generators (PRGs) of the shift register type for cycling the addresses and data pseudo-randomly.

First, the address and data registers are initialized and cycled in the write mode. Unique data patterns are thereby written into each location in the array. Next, the address and data registers are again initialized and cycled in the read mode. The output data from the array are compared to the data register contents, the comparator output signal being observed for error indications.

If the self-testing embedded array is modified as shown in the figure, then during the read-out portion of the test, a correct compare will cause no change in the output from the comparator. An incorrect comparison, however, will cause a logical one signal in the feedback loop, changing the count in the PRG. If all comparisons are correct, the same correct data register contents will remain when scanned out.

This technique has the advantage that an observation is not required on the primary output each time the array is read and compared to the data register contents. This is done internally and observed after the test, resulting in a high- speed, self-testing function. References [1] U.S. Patent 3,614,400. [2] R. A. Frohwerk, "Signature Analysis: A New Digital Field Service Method," Hewlett- Packard Journal, May, 1977, pp. 2-8. [3] S. W. Golomb, Shift Re...