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Low Power Inverter Driver Circuit

IP.com Disclosure Number: IPCOM000051324D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Erdelyi, CK: AUTHOR

Abstract

This field-effect transistor circuit enables the reduction in power of up to 60% of that consumed by the saturated depletion load device inverter shown in Fig. 1.

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Low Power Inverter Driver Circuit

This field-effect transistor circuit enables the reduction in power of up to 60% of that consumed by the saturated depletion load device inverter shown in Fig. 1.

Fig. 2 illustrates a split-load inverter driver including enhancement device T1 responsive to input signal Vin, depletion device T2 connected between drain supply voltage Vd and output Vout and having its gate connected to the drain of T1. Depletion device T3 is connected between Vout and the drain of T1 and has its gate connected to Vout. T3 turns off pull-up device T2 during downward transitions of Vout and acts to limit the DC current of the circuit when Vin is high. By varying the width-to-length ratio of T3 from 1:1 to 1:3, power consumption of from 61.5 to 45% of that of the circuit of Fig. 1 is obtained.

The split-load circuit can also be used in logic circuits, such as NOR or NAND circuits.

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