Browse Prior Art Database

Detection of Single Bit Failures using In Memories Using Longitudinal Parity

IP.com Disclosure Number: IPCOM000051326D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Linton, RH: AUTHOR

Abstract

This error detection system uses existing sensing schemes of a dynamic memory to implement a longitudinal parity checking system without substantial impact on system performance. It is particularly suitable for error correction of soft errors caused by radiation, such as alpha particles.

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Detection of Single Bit Failures using In Memories Using Longitudinal Parity

This error detection system uses existing sensing schemes of a dynamic memory to implement a longitudinal parity checking system without substantial impact on system performance. It is particularly suitable for error correction of soft errors caused by radiation, such as alpha particles.

Dynamic semiconductor random access memories are organized as a m x n matrix of words x bits, as shown in the figure. In memories of this type a read operation is performed by selecting or decoding a single word line 10 and sensing the accessed data associated with n bit lines 12 simultaneously. Data from one of the bit lines is transferred as a single bit of output data through a bit decoder to data input/output circuitry (not shown).

By providing one additional data bit line 14 and its associated memory cells, a parity bit can be stored for all of the bits associated with each word line on the memory chip. One additional sense amplifier 16 is provided to sense the parity bit each time a word is accessed. Coupled to each of the n+1 bit lines is a parallel load, serial shift register 18, having a single data output terminal.

The data read from each bit line selected during a read cycle is loaded into shift register 18 in addition to being applied to the normal bit decoder. When a parity check or error is detected external to the memory chip by suitable logic, the possibility exists that the single data bit provided by a particular memory chip was in error. To determine which memory chip provided the err...