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Browse Prior Art Database

Threshold Independent Chip Select Input Circuit

IP.com Disclosure Number: IPCOM000051328D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Lewis, SC: AUTHOR

Abstract

This circuit avoids the signal loss due to FET device threshold voltage tolerance found in grounded source inverter drivers typically used for transistor-transistor logic (TTL) input responsive circuits. This problem is a particular concern when the TTL input signal low level may exceed the input device threshold voltage and where the TTL up level is so low that the difference in gate drive between the high and low input levels is very small.

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Threshold Independent Chip Select Input Circuit

This circuit avoids the signal loss due to FET device threshold voltage tolerance found in grounded source inverter drivers typically used for transistor- transistor logic (TTL) input responsive circuits. This problem is a particular concern when the TTL input signal low level may exceed the input device threshold voltage and where the TTL up level is so low that the difference in gate drive between the high and low input levels is very small.

The circuit of Fig. 1 provides a buffer circuit between the TTL input CS and the gate of the grounded source device T1 which provides a signal at node B approximately equal to Vt + CS - CS min, where Vt is the threshold voltage of T2. This provides zero volts overdrive on T1 when CS is low, i.e., about 0.8 volt, and
1.4 volts overdrive when CS is up, i.e., about 2.2 volts.

Referring to Fig. 1, voltage node A is driven by constant current source 10 from FET drain supply voltage source VH. Since this current is discharged through voltage source 12 and T2 to the TTL input, the constant current Ic is made as small as practical, for example, 0.2 milliamp. Assuming T2 is large and provides little of the voltage drop between VH and input CS, voltage node A will be at Vt(T2) + CS -V, where V is chosen to be the same voltage as the TTL low input level. The voltage on node B will now vary between Vt and Vt + CS (high) - CS (low).

Implementation of the circuit in integrated circuit compo...