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High Throughput Logic

IP.com Disclosure Number: IPCOM000051333D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Rhodes, KE: AUTHOR

Abstract

A test sequence comprising groups of coherent subsequences is performed rapidly by storing, with each test instruction in the sequence, the address for the next instruction in the sequence if the test is passed and, in addition, the address for an alternate next instruction should the test not be passed. This technique is particularly useful in routines such as the matrix or feature examination of a character image for character recognition, since each instruction contains the information necessary to immediately bypass subsequent tests which become unnecessary due to the passing or failure of any particular test.

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High Throughput Logic

A test sequence comprising groups of coherent subsequences is performed rapidly by storing, with each test instruction in the sequence, the address for the next instruction in the sequence if the test is passed and, in addition, the address for an alternate next instruction should the test not be passed. This technique is particularly useful in routines such as the matrix or feature examination of a character image for character recognition, since each instruction contains the information necessary to immediately bypass subsequent tests which become unnecessary due to the passing or failure of any particular test.

A test sequence store 1 provides a series of address locations 2 each containing a test instruction 3. A particular test instruction 3 is specified by an address applied to store address register 4. Each test instruction 3 contains a next address field 5, an alternate next address field 6, a test object address 7, a test condition field 8, and a subsequence step field 9.

The digitized image of a character to be identified is loaded into test subject store 10 in a form, for example, such that logical "1" represents black, or image regions, and logical "0" represents white, or background regions. The test sequence examines the data thus loaded into memory 10 for the presence or absence of 1's and 0's at significant locations and in significant combinations. To this end, the address contained in instruction field 7 specifies a particu...