Browse Prior Art Database

Optical Emitter with Processor Control

IP.com Disclosure Number: IPCOM000051345D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Arnold, RW: AUTHOR [+3]

Abstract

A microprocessor can adjust multiple channels, provide comparative historical performance data and improve stability for feedback optical emitters.

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Optical Emitter with Processor Control

A microprocessor can adjust multiple channels, provide comparative historical performance data and improve stability for feedback optical emitters.

Referring to Fig. 1, a microprocessor 1 is attached through a peripheral interface adapter (PIA) 2 to channels A and B of an optical emitter circuit. Each channel includes a light-emitting diode (LED) and mating phototransistor (PTX) that may be arranged about a common disk having a single band of opaque and transparent areas. The portion of channel A enclosed by broken line is identical to channel B. Logic at the right of the figure is common to both channels. Eight- bit digital values are provided from the microprocessor 1 through PIA 2 to an octal polarity latch 3 and digital-to-analog converter 4. The converter output is supplied to amplifier 5 whose output controls transistor 6 to govern current through LED 7. A feedback circuit of capacitor 8 and resistor 9 integrates the digital-to-analog converter output to prevent glitches. Light interruptions by the opaque marks 10 of disk 11 are sensed at PTX 12. Its output is connected as an input to operational amplifier 13. The amplified output signal serves as an input to operational amplifier 14 and comparator 15 for respectively providing square- wave timing signal outputs and determining changes in the signal level. The reference voltage for operational amplifier 14 is held as a proportion of the output of operational amplifier 13 whose reference V1 also tracks that of VH.

The two channels are monitored alternately by conditioning one of two AND circuits 16 and 17, each of which is respectively operable to set or reset latch 18. The output of latch 18 conditions either AND gate 19 or 20. These gates are each respectively connected to the Channel A High output latch 21 or Channel B High output latch on line 22. Thus, depending upon the channel conditioned by PIA 2, the output is provided by gate 24. This signal can be used as an input to the PIA and microprocessor to increment or decrement the value supplied to the respective octal polarity latches 3 for the two channels.

An example of a subroutine for checking the emitter channels is shown in Fig. 2. The routine uses a timer to prevent the loop from continually looking for transitions when there is a system error, such as a st...