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Browse Prior Art Database

Power Efficient Cascode Logic

IP.com Disclosure Number: IPCOM000051346D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Nosowicz, EJ: AUTHOR [+2]

Abstract

It can be shown that both high function logic element D (Fig. 1) or lo (or unit) function logic elements B, C may be combined in a power-efficient manner by stacking the unit function elements or blocks B and C in series with the power supply (not shown). This arrangement provides system advantages which expedite the realization of the total logic function E. Assume, for example, that the high function logic block D is a multilevel cascode current switch and that low function logic blocks B and C are single or two level current switches. It will be noted then that B interfaces easily with the upper level inputs and outputs of D. Logic block C interfaces easily with the lower level inputs of D, but interfaces with somewhat more difficulty with the outputs of D which are at the upper level.

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Power Efficient Cascode Logic

It can be shown that both high function logic element D (Fig. 1) or lo (or unit) function logic elements B, C may be combined in a power-efficient manner by stacking the unit function elements or blocks B and C in series with the power supply (not shown). This arrangement provides system advantages which expedite the realization of the total logic function E. Assume, for example, that the high function logic block D is a multilevel cascode current switch and that low function logic blocks B and C are single or two level current switches. It will be noted then that B interfaces easily with the upper level inputs and outputs of D. Logic block C interfaces easily with the lower level inputs of D, but interfaces with somewhat more difficulty with the outputs of D which are at the upper level. It should also be noted that read-only storage (ROS) and random-access memory (RAM) functions are typically low voltage functions and could be located at either B or C.

Fig. 2 shows how this may be used to advantage in a logic function such as a microcomputer. Many of these applications require selection of a data path or function followed by high speed manipulation of data. This fits cascode logic where most function selection is done in the lower levels and data manipulation in the faster upper levels. The upper levels would interface with data handling unit logic and any on-chip RAM. The ROS, which forms the control, would be located in the lower...