Browse Prior Art Database

Etchback Planarization Process

IP.com Disclosure Number: IPCOM000051366D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Bartush, TA: AUTHOR [+2]

Abstract

A quartz dielectric layer for integrated circuit metallurgy is planarized by a dual-resist coat and plasma etchback process.

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Etchback Planarization Process

A quartz dielectric layer for integrated circuit metallurgy is planarized by a dual-resist coat and plasma etchback process.

The prior etchback process which uses a single coat of photoresist, has drawbacks in that large (greater than 10 mu) horizontal dimensions of quartz over wide metal lands are difficult to planarize. Overetching for long periods of time is necessary to remove the residual quartz from these wide metal lands, and subsequently the quartz insulator is thinned to a dangerous point on other parts of the chip.

A process sequence solves this problem by intentionally changing the thickness of the resist over these wide patterns.

As illustrated in Fig. 1, when planarized quartz 1 is deposited over metal patterns, the thickness of the quartz will change from a few thousand angstroms over narrow metal geometries 2 (6 mu) to a maximum over wide metal geometries 3 (greater than 10 mu) on substrate 4.

A coating 5 of photoresist is applied over the surface to be planarized. The thickness of this coating should be approximately 1.5 times the thickness of the quartz insulator 1. The resist is then exposed using exactly the same pattern which was used to define the metal pattern. The resist is developed and cross- linked, and the resist layer 5 will be patterned as illustrated in Fig. 2.

A second coating of resist is now applied to form a composite coating 6. This second coating should be thinner than the quartz insulator thickne...