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Browse Prior Art Database

Static Ram Double Polysilicon Process

IP.com Disclosure Number: IPCOM000051371D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 134K

Publishing Venue

IBM

Related People

Baran, AS: AUTHOR [+6]

Abstract

This process allows static components such as high sheet rho polysilico resistors to be formed over active insulated gate field-effect transistor devices and stacking contacts on top of each other. The process is a modification of the conventional double polycrystalline silicon process and requires one additional mask.

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Static Ram Double Polysilicon Process

This process allows static components such as high sheet rho polysilico resistors to be formed over active insulated gate field-effect transistor devices and stacking contacts on top of each other. The process is a modification of the conventional double polycrystalline silicon process and requires one additional mask.

The first photolithography operation is the recess oxide isolation (ROX) or channel stop, as shown in Fig. 1. The next photolithography step is the buried contact step in which openings, as shown in Fig. 2, are provided in the silicon dioxide layer 10 in areas designated for the polycrystalline silicon to contact the silicon substrate. In Fig. 3, the first polycrystalline silicon layer 12, having low sheet rho, is shown following etching. The source and drain doping via open tube thermal diffusion or ion implantation is done followed by a source and drain reoxidation to produce silicon dioxide layer 14 in which the silicon dioxide grown is much greater in thickness than the gate silicon dioxide layer 10.

The use of a doping step prior to the second polysilicon deposition allows the second polycrystalline silicon layer 18 to be on top of the first polycrystalline layer 12 active device without introducing parasitic transistor operation over non-ROX regions, as seen in Fig. 4. The next operation is a contact lithographic operation, as shown in Fig. 5. This allows the second polycrystalline silicon layer 18 to contact first polycrystalline silicon 12. Metal silicide contacts 16 may be directly on top of layer 12 buried contacts, as shown in Fig. 5. This ste...