Browse Prior Art Database

Deep Dielectric Isolation

IP.com Disclosure Number: IPCOM000051373D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Riseman, J: AUTHOR

Abstract

The complete dielectric isolation structure of Fig. 1, wherein mono-crystalline silicon regions 5 are isolated from one another by silicon dioxide regions 6 and a polycrystalline silicon backing or handle 7 comprises the remainder of the body, may be produced by known methods. Briefly, such a method includes silicon dioxide masking a mono-crystalline silicon wafer and etching the mono-crystalline silicon 5 in areas where the dielectric isolation is planned. The etched regions are subjected to an oxidation ambient to form silicon dioxide regions 6 over the surfaces. Polycrystalline silicon 7 is deposited over the silicon dioxide layer to form the handle. The back of the original wafer is lapped away until the original silicon dioxide is reached. Fig. 1 shows this structure with the surface silicon dioxide layer removed.

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Deep Dielectric Isolation

The complete dielectric isolation structure of Fig. 1, wherein mono-crystalline silicon regions 5 are isolated from one another by silicon dioxide regions 6 and a polycrystalline silicon backing or handle 7 comprises the remainder of the body, may be produced by known methods. Briefly, such a method includes silicon dioxide masking a mono-crystalline silicon wafer and etching the mono- crystalline silicon 5 in areas where the dielectric isolation is planned. The etched regions are subjected to an oxidation ambient to form silicon dioxide regions 6 over the surfaces. Polycrystalline silicon 7 is deposited over the silicon dioxide layer to form the handle. The back of the original wafer is lapped away until the original silicon dioxide is reached. Fig. 1 shows this structure with the surface silicon dioxide layer removed.

Two dashed lines are shown where the isolation regions are deliberately reached (8) in the backlapping, polishing or etching and where the isolation regions are deliberately not reached (9). These lines are shown not parallel to the starting surface to indicate that the resultant surface need not be parallel thereto. These surfaces are the reference surface. The reference surface is implanted or diffused to form a N+ subcollector 10 (Fig. 2). An epitaxial layer 11 is grown on the surface of subcollector 10. The thickness of layer 11 may be one micron, for example. In the case of line 8, the silicon will be polycrystalline...