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Bipolar Transistor having Low Base Collector Junction and Diffusion Capacitances

IP.com Disclosure Number: IPCOM000051388D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+3]

Abstract

High performance transistors require minimized base-collector junction capacitance and diffusion capacitance due to base-widening and charge storage in the collector region. Such minimization is achieved in a pedestal collector bipolar transistor made by the process described below.

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Bipolar Transistor having Low Base Collector Junction and Diffusion Capacitances

High performance transistors require minimized base-collector junction capacitance and diffusion capacitance due to base-widening and charge storage in the collector region. Such minimization is achieved in a pedestal collector bipolar transistor made by the process described below.

N/ / subcollector 1 is placed into P substrate 2, and N epitaxial layer 3 is grown. P polycrystalline layer 4 is deposited over epi 3. Oxide layer 5 is deposited over layer 4, and layers 4 and 5 are patterned as shown in Fig. 1. Arsenic or phosphorous is blanket implanted to produce N/+/ pedestal 6 on subcollector 1.

A thin thermal screen oxide is grown over the structure, and base dopant is ion implanted into region 7 of Fig. 2. The emitter is ion implanted into region 8, and all dopants are driven in by thermal annealing during which the P impurity outdiffuses from polycrystalline layer 4 to form extrinsic base region 9. The device is completed by adding contacts (not shown) to the emitter region 8, /+/P extrinsic base 9 and collector reach-through 10.

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