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T/2/L Receiver Circuit

IP.com Disclosure Number: IPCOM000051391D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Bass, A: AUTHOR [+4]

Abstract

The receiver circuit shown in Fig. 1 has improved down-level noise margin over a prior-art receiver circuit, as depicted in Fig. 2. The improvement is accomplished by introducing a separate base supply VB which is raised relative to the collector supply VC.

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T/2/L Receiver Circuit

The receiver circuit shown in Fig. 1 has improved down-level noise margin over a prior-art receiver circuit, as depicted in Fig. 2. The improvement is accomplished by introducing a separate base supply VB which is raised relative to the collector supply VC.

Fig. 3 shows a circuit which supplies the elevated VB voltage.

The output VB of the circuit is taken from transistors T1 and T2, arranged in a Darlington configuration for very low output impedance.

Schottky barrier diodes D1 and D2 are connected in parallel, as are D3 and D4. Also, transistors T3, T4 and T5 are wired as diodes and connected in parallel. Thus, the base of T1 is biased to a voltage equal to two Schottky diode drops plus a base-emitter drop above VC. The output VB is then two base-emitter drops below the base of T1. The significant result of this circuit is that VB has low impedance and is always higher than VC by the difference between two Schottky diode drops and one base-emitter drop.

In practice, VC is 1.7 volts and VB is higher than VC by about 0.3 volt. The receiver noise margin is increased by about 0.2 volt.

Fig. 4 shows worst-case pulse width versus amplitude curves for both the improved and the prior-art receiver circuits in the down-level state.

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