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Method of Optimized Test Pattern Generation for Logic Circuits

IP.com Disclosure Number: IPCOM000051392D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Goel, P: AUTHOR

Abstract

This method automates the choice and the switching of combinations of test generation tools to achieve a desired test generation performance for a logic circuit under test. Among the test generation tools that are combined for optimized test pattern generation are RANDOM [1], RAPS [2], DALG [3], test pattern subsumation [4], and fault simulation [5]. The method incorporates (a) monitoring the performance of test generation processes, (b) automatic initiation and switching of different combinations of test generation tools, (c) generating a measurement of test time per detected fault as a first performance factor, and (d) generating a measurement of detected faults per test as a second performance factor.

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Method of Optimized Test Pattern Generation for Logic Circuits

This method automates the choice and the switching of combinations of test generation tools to achieve a desired test generation performance for a logic circuit under test. Among the test generation tools that are combined for optimized test pattern generation are RANDOM [1], RAPS [2], DALG [3], test pattern subsumation [4], and fault simulation [5]. The method incorporates (a) monitoring the performance of test generation processes, (b) automatic initiation and switching of different combinations of test generation tools, (c) generating a measurement of test time per detected fault as a first performance factor, and (d) generating a measurement of detected faults per test as a second performance factor.

The following parameters are defined to establish performance factors FT and CF (defined below), for a logic circuit under test: FT (faults per test) = U over T.

CF (CPU time per fault) = C over U.

T - The number of independent tests that should be generated to test all of the as yet untested faults in the logic circuit. for yet untested faults.

U - The number of untested faults at a given instant in the test generation process.

The program begins by establishing a table in memory for (1) different combinations of test generation tools or strategies (referred to as Table 1) and
(2) a controlled program that implements the flow diagram shown in the figure.

In Step 1 of the program, a variable i is set to 1. In Step 2, i is compared to the number of strategies in Table 1. If i is greater than the number of strategies in Table 1, the program exits. If i is less than the number of strategies in Table 1, then an unused strategy in Table 1 is selected from the Table 1 in Step 3. The selected test strategy is exercised to generate at least ten test generation patterns in Step 4. The actual test generation performance is determined over the ten tests in order to smooth out local variations. The choice of ten is arbitrary. In an actual implementation, the performance is checked whenever a total of ten instances of successful test generation or failures to generate a test pattern occurs. This procedure insures performance checks even when the system is relatively unsuccessful in test generation. At the completion of the ten test generation passes, a first compare is done at Step 5 to det...