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Browse Prior Art Database

MTL/I/2/L Storage Cell

IP.com Disclosure Number: IPCOM000051397D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Schmitt, A: AUTHOR

Abstract

The storage cell consists of two inverter stages cross-coupled in the manner of a flip-flop. Each inverter stage corresponds to a merged transistor logic (MTL)/integrated injection logic (I/2/L) basic structure with injection zones P1 and P1' arranged laterally to inversely operated vertical, Inverting transistors T2 and T2', respectively. Injection zones P1, P1', which are merged with the zones of inverting transistors T2, T2', form lateral transistors T1, T1' with the zone sequence P1N1P2 (P1'N1'P2'). The supply of the operating current and the coupling of the read/write signals are effected via a bit line pair B0, B1 connected to injection zones P1 and P1', respectively. For addressing, an address line X is connected to the common emitters N1, N1' of inverting transistors T2, T2'.

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MTL/I/2/L Storage Cell

The storage cell consists of two inverter stages cross-coupled in the manner of a flip-flop. Each inverter stage corresponds to a merged transistor logic (MTL)/integrated injection logic (I/2/L) basic structure with injection zones P1 and P1' arranged laterally to inversely operated vertical, Inverting transistors T2 and T2', respectively. Injection zones P1, P1', which are merged with the zones of inverting transistors T2, T2', form lateral transistors T1, T1' with the zone sequence P1N1P2 (P1'N1'P2'). The supply of the operating current and the coupling of the read/write signals are effected via a bit line pair B0, B1 connected to injection zones P1 and P1', respectively. For addressing, an address line X is connected to the common emitters N1, N1' of inverting transistors T2, T2'. The current injected back into the appertaining injection zone P1, P1', when inverting transistor T2 or T2' is conductive, is used during reading.

Fig. 1 is an equivalent circuit diagram of the storage cell. Fig. 2 is a sectional view of a conventionally designed MTL/I/2/L basic structure after an intermediate process step in which contact mask M is deposited.

As basic material, a lightly doped semiconductor substrate P- is used. A highly doped buried zone N+ (subemitter of T2) of the opposite conductivity type is arranged on top of the semiconductor substrate. The buried zone N+ is followed by an N doped epitaxial layer N1. Two zones P1 (injection zone) and P2...